1. Field of the Invention
This invention generally relates to integrated circuit (IC) design and, more particularly, to a method for allocating timing delay budgets across IC modules using gate-delay and wire-distance estimates.
2. Description of the Related Art
The size, complexity, and operating or switching speeds of semiconductor ICs have increased, while feature geometries have decreased, and interconnect systems for such ICs have dramatically increased in complexity. In a digital circuit, data is supposed to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock.
As noted in Wikipedia, one approach that is used to analyze timing errors is to model the interconnect system as an arrangement of nets (interconnections between gate outputs and interconnected gate inputs) inter-coupled with parasitic capacitors. Static Timing Analysis (STA) is used to develop early and late arrival times (timing window) for each relevant net or node. This timing window is enlarged by a worst case assessment of crosstalk noise for both early and late arrival times using noise aware STA. This worst case timing window is used for timing analysis of all paths through the corresponding net and a list of paths that fail timing requirements are provided. In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations.
More explicitly, STA is a method of computing the expected timing of a digital circuit without performing a simulation. High-performance ICs have conventionally been characterized by the clock frequency at which they operate. Gauging the operation of a circuit at a specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculations must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Faster design times are a result of using simplified STA delay models, and a limited consideration of the effects of logical interactions between signals.
One problem with STA is that the analysis can only be performed after the design and layout of a digital circuit. However, before the design is started, some estimations must be made to aid in the budgeting of time inside modules and between modules. Typically, module level time-budgeting is done manually or at a later stage in the design-cycle, when the contents and the details of the sub-modules are better known. By then, it may be too late to change the micro-architecture without impacting the design and schedule.
It would be advantageous if there was a means of creating timing budget estimates based upon on an early floor-plan, to insure that the modules in an IC are designed to realistic timing specifications.